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商品詳細
Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them. 2007 ed.
・ISBN 978-0-387-71714-2 hard EUR 169.99
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| 著者・編者 | Sutherland, Stuart / Mills, Don, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2007 |
| ページ数 | 218 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-50365＞ |
解説
In programming, "Gotcha" is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly.
This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors.
This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.