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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling. Softcover reprint of the original 1st ed. 2014
・ISBN 978-1-4939-4817-8 paper EUR 99.99
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お気に入り
★★★
| 著者・編者 | Mandal, Ayan / Khatri, Sunil P. / Mahapatra, Rabi, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2016 |
| ページ数 | 143 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-48592＞ |
解説
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.