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商品詳細
Multi-Net Optimization of VLSI Interconnect. Softcover reprint of the original 1st ed. 2015
・ISBN 978-1-4939-4262-6 paper EUR 89.99
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| 著者・編者 | Moiseev, Konstantin / Kolodny, Avinoam / Wimer, Shmuel, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2016 |
| ページ数 | 233 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-48400＞ |
解説
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.