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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.
・ISBN 978-3-319-02377-9 hard EUR 99.99
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お気に入り
★★★
| 著者・編者 | Noia, Brandon / Chakrabarty, Krishnendu, |
|---|---|
| 出版社 | (Springer International Publishing AG, SZ) |
| 出版年月 | 2013 |
| ページ数 | 245 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-46346＞ |
解説
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.