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The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ- ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif- ferent conversion techniques applicable in this range of sample rates is dis- cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi- zation of capacitor sizes, design of low-voltage transmission gates, and opti- mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech- niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.