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Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Softcover reprint of the original 1st ed. 2003
・ISBN 978-1-4419-5402-2 paper EUR 99.99
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| 著者・編者 | Radecka, Katarzyna / Zilic, Zeljko, |
|---|---|
| シリーズ | (Frontiers in Electronic Testing) |
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2010 |
| ページ数 | 216 pp. |
| 言語 | ENG |
| ニュース番号 | <A05-44758> |
解説
1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.