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商品詳細
Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC). 2013 ed.
・ISBN 978-1-4899-8916-1 paper EUR 99.99
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お気に入り
★★★
| 著者・編者 | Gangadharan, Sridhar / Churiwala, Sanjay, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2015 |
| ページ数 | 226 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-39165＞ |
解説
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.