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商品詳細
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring. 2008 ed.
・ISBN 978-1-4020-8585-7 hard EUR 99.99
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| 著者・編者 | Boule, Marc / Zilic, Zeljko, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2008 |
| ページ数 | 280 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-36367＞ |
解説
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.
This is the first book that presents an "under-the-hood" view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.