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System-on-a-Chip Verification: Methodology and Techniques. Softcover reprint of the original 1st ed. 2001
・ISBN 978-1-4757-7468-9 paper EUR 159.99
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| 著者・編者 | Rashinkar, Prakash / Paterson, Peter / Singh, Leena, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2013 |
| ページ数 | 372 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-34374＞ |
解説
System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
- Explanation of the objective involved in performing verification after a given design step;
- Features of options available;
- When to use a particular option;
- How to select an option; and
- Limitations of the option.