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商品詳細
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches. Previously published in hardcover
・ISBN 978-1-4614-2505-2 paper
| 著者・編者 | Jespers, Paul, |
|---|---|
| シリーズ | (Analog Circuits and Signal Processing) |
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2012 |
| ページ数 | 171 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A05-27653＞ |
解説
In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.