株式会社極東書店トップ商品一覧Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Softcover reprint of the original 1st ed. 1991

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Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Softcover reprint of the original 1st ed. 1991

Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Softcover reprint of the original 1st ed. 1991

・ISBN 978-1-4613-6768-0 paper EUR 99.99

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お気に入り
著者・編者McGeer, Patrick C. / Brayton, Robert K.,
シリーズ (The Springer International Series in Engineering and Computer Science)
出版社 (Springer-Verlag New York Inc., US)
出版年月2012
ページ数212 pp.
言語ENG
ニュース番号<A04-86273>

解説

This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under- estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu- racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo- ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.