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Integrated Circuit Defect-Sensitivity: Theory and Computational Models. Softcover reprint of the original 1st ed. 1993
・ISBN 978-1-4613-6383-5 paper EUR 99.99
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| 著者・編者 | Pineda de Gyvez, Jose, |
|---|---|
| シリーズ | (The Springer International Series in Engineering and Computer Science) |
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2014 |
| ページ数 | 167 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A04-83439＞ |
解説
The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.