株式会社極東書店トップ ＞ 商品一覧 ＞ High-Level Power Analysis and Optimization. Softcover reprint of the original 1st ed. 1998
商品詳細
High-Level Power Analysis and Optimization. Softcover reprint of the original 1st ed. 1998
・ISBN 978-1-4613-7481-7 paper EUR 99.99
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お気に入り
★★★
| 著者・編者 | Raghunathan, Anand / Jha, Niraj K. / Dey, Sujit, |
|---|---|
| 出版社 | (Springer-Verlag New York Inc., US) |
| 出版年月 | 2012 |
| ページ数 | 175 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A04-80570＞ |
解説
High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.