株式会社極東書店トップ ＞ 商品一覧 ＞ Low-Power Design and Power-Aware Verification. 1st ed. 2018
商品詳細
Low-Power Design and Power-Aware Verification. 1st ed. 2018
・ISBN 978-3-319-66618-1 hard EUR 139.99
￥37,418.- (税込) ※（※）価格はご注文時の参考価格となります。
納品価格につきましては書籍の入荷時点で確定となります。
版元の原価改定、外国為替の変動等により異なる場合がございますので、予めご了承下さい。
| 著者・編者 | Khondkar, Progyna, |
|---|---|
| 出版社 | (Springer International Publishing AG, SZ) |
| 出版年月 | 2017 |
| ページ数 | 155 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A02-90713＞ |
解説
Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base.
LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination.
The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r
egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.