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商品詳細
Parasitic Substrate Coupling in High Voltage Integrated Circuits: Minority and Majority Carriers Propagation in Semiconductor Substrate. 2018 ed.
・ISBN 978-3-319-74381-3 hard EUR 99.99
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| 著者・編者 | Buccella, Pietro / Stefanucci, Camillo / Kayal, Maher / Sallese, Jean-Michel, |
|---|---|
| シリーズ | (Analog Circuits and Signal Processing) |
| 出版社 | (Springer International Publishing AG, SZ) |
| 出版年月 | 2018 |
| ページ数 | 183 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A02-75357＞ |
解説
This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
- Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
- Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
- Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
- Offers design guidelines to reduce couplings by adding specific protections.