株式会社極東書店トップ ＞ 商品一覧 ＞ ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. 1st ed. 2018
商品詳細
ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. 1st ed. 2018
・ISBN 978-3-319-59417-0 hard EUR 149.99
￥40,091.- (税込) ※（※）価格はご注文時の参考価格となります。
納品価格につきましては書籍の入荷時点で確定となります。
版元の原価改定、外国為替の変動等により異なる場合がございますので、予めご了承下さい。
お気に入り
★★★
| 著者・編者 | Mehta, Ashok B., |
|---|---|
| 出版社 | (Springer International Publishing AG, SZ) |
| 出版年月 | 2017 |
| ページ数 | 328 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A02-38034＞ |
解説
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies.