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A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof. 2020 ed.
・ISBN 978-3-030-43242-3 paper EUR 49.99
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| 著者・編者 | Lutsyk, Petro / Oberhauser, Jonas / Paul, Wolfgang J., |
|---|---|
| シリーズ | (Lecture Notes in Computer Science) |
| 出版社 | (Springer Nature Switzerland AG, SZ) |
| 出版年月 | 2020 |
| ページ数 | 628 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A01-84774＞ |
解説
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Mueller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
* MIPS instruction set architecture (ISA) for application and for system programming
* cache coherent memory system
* store buffers in front of the data caches
* interrupts and exceptions
* memory management units (MMUs)* pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
* local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
* I/O-interrupt controller and a disk