株式会社極東書店トップ ＞ 商品一覧 ＞ System Level Design from HW/SW to Memory for Embedded Systems: 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguacu, Brazil, November 3-6, 2015, Proceedings. 2017 ed.
商品詳細
System Level Design from HW/SW to Memory for Embedded Systems: 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguacu, Brazil, November 3-6, 2015, Proceedings. 2017 ed.
・ISBN 978-3-319-90022-3 hard EUR 49.99
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| 著者・編者 | Goetz, Marcelo / Schirner, Gunar / Wehrmeister, Marco Aurelio / Al Faruque, Mohammad Abdullah / Rettberg, Achim (eds.), |
|---|---|
| シリーズ | (IFIP Advances in Information and Communication Technology) |
| 出版社 | (Springer International Publishing AG, SZ) |
| 出版年月 | 2018 |
| ページ数 | 231 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A01-92522＞ |
解説
This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguacu, Brazil, in November 2015.
The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.