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商品詳細
Completion Detection in Asynchronous Circuits: Toward Solution of Clock-Related Design Challenges. 2022 ed.
・ISBN 978-3-031-18399-7 paper EUR 84.99
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| 著者・編者 | Srivastava, Pallavi, |
|---|---|
| 出版社 | (Springer International Publishing AG, SZ) |
| 出版年月 | 2023 |
| ページ数 | 119 pp. |
| 言語 | ENG |
| ニュース番号 | ＜A01-90923＞ |
解説
This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.