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Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level.
・ISBN 978-1-108-49454-0 hard GB£ 74.99
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★★★
| 著者・編者 | Razavi, Behzad, |
|---|---|
| 出版社 | (Cambridge University Press, UK) |
| 出版年月 | 2020 |
| ページ数 | 506 pp. |
| 言語 | ENG |
| ニュース番号 | <A00-22202> |
解説
Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.